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1 ? fn7106.2 el8202, el8203, EL8403 500mhz rail-to-rail amplifiers the el8202, el8203, and EL8403 represent rail-to-rail amplifiers with a -3db bandwidth of 500mhz and slew rate of 600v/s. running off a very low supply current of 5.6ma per channel, the el8202, el8203, and EL8403 also feature inputs that go to 0.15v below the v s - rail. the el8202 and el8203 are dual channel amplifiers. the EL8403 is a quad channel amplifier. the el8202 includes a fast-acting disable/power-down circuit. with a 25ns disable and a 200ns enable, the el8202 is ideal for multiplexing applications. the el8202, el8203, and EL8403 are designed for a number of general purpose video, communication, instrumentation, and industrial applications. the el8202 is available in a 10 ld msop package, the el8203 in 8 ld so and 8 ld msop packages, and the EL8403 in 14 ld so and 16 ld qsop packages. all are specified for operation over the -40c to +85c temperature range. features ? 500mhz -3db bandwidth ? 600v/s slew rate ? low supply current = 5.6ma per channel ? supplies from 3v to 5.5v ? rail-to-rail output ? input to 0.15v below v s - ? fast 25ns disable (el8202 only) ?low cost ? pb-free plus anneal available (rohs compliant) applications ? video amplifiers ? portable/hand-held products ? communications devices ordering information part number part marking tape & reel package pkg. dwg. # el8202iy m - 10 ld msop mdp0043 el8202iy-t7 m 7? 10 ld msop mdp0043 el8202iy-t13 m 13? 10 ld msop mdp0043 el8202iyz (see note) bapaa - 10 ld msop (pb-free) mdp0043 el8202iyz-t7 (see note) bapaa 7? 10 ld msop (pb-free) mdp0043 el8202iyz-t13 (see note) bapaa 13? 10 ld msop (pb-free) mdp0043 el8203is 8203is - 8 ld so mdp0027 el8203is-t7 8203is 7? 8 ld so mdp0027 el8203is-t13 8203is 13? 8 ld so mdp0027 el8203isz (see note) 8203isz - 8 ld so (pb-free) mdp0027 el8203isz-t7 (see note) 8203isz 7? 8 ld so (pb-free) mdp0027 el8203isz-t13 (see note) 8203isz 13? 8 ld so (pb-free) mdp0027 el8203iy bjaaa - 8 ld msop mdp0043 el8203iy-t7 bjaaa 7? 8 ld msop mdp0043 el8203iy-t13 bjaaa 13? 8 ld msop mdp0043 EL8403is 8403is - 14 ld so mdp0027 EL8403is-t7 8403is 7? 14 ld so mdp0027 EL8403is-t13 8403is 13? 14 ld so mdp0027 EL8403isz (see note) 8403isz - 14 ld so (pb-free) mdp0027 EL8403isz-t7 (see note) 8403isz 7? 14 ld so (pb-free) mdp0027 EL8403isz-t13 (see note) 8403isz 13? 14 ld so (pb-free) mdp0027 EL8403iu 8403iu - 16 ld qsop mdp0040 EL8403iu-t7 8403iu 7? 16 ld qsop mdp0040 EL8403iu-t13 8403iu 13? 16 ld qsop mdp0040 EL8403iuz (see note) 8403iuz - 16 ld qsop (pb-free) mdp0040 EL8403iuz-t7 (see note) 8403iuz 7? 16 ld qsop (pb-free) mdp0040 EL8403iuz-t13 (see note) 8403iuz 13? 16 ld qsop (pb-free) mdp0040 note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number part marking tape & reel package pkg. dwg. # data sheet april 26, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003, 2006. all rights reserved. all other trademarks mentioned are the property of their respective owners.
2 pinouts el8202 (10 ld msop) top view el8203 (8 ld so, msop) top view EL8403 (14 ld so) top view EL8403 (16 ld qsop) top view - + - + ina+ cea vs- ceb ina- outa vs+ outb inb+ inb- 1 2 3 4 10 9 8 7 5 6 1 2 3 4 8 7 6 5 - + - + outa ina- ina+ vs- vs+ outb inb- inb+ 1 2 3 4 14 13 12 11 5 6 7 10 9 8 outa ina- ina+ vs+ inb+ inb- outb outd ind- ind+ vs- inc+ inc- outc -+ - + -+ - + ad bc 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 outa ina- ina+ vs+ inb+ inb- outb outd ind- ind+ vs- inc+ inc- outc nc nc -+ - + -+ - + el8202, el8203, EL8403
3 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maxi mum ratings (t a = 25c) supply voltage from v s + to v s - . . . . . . . . . . . . . . . . . . . . . . . . 5.5v input voltage . . . . . . . . . . . . . . . . . . . . . . . . v s + +0.3v to v s - -0.3v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v continuous output current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ma power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v s + = 5v, v s - = gnd, t a = 25c, v cm = 2.5v, r l to 2.5v, a v = 1, unless otherwise specified parameter description conditions min typ max unit input characteristics v os offset voltage -8 -0.8 +8 mv tcv os offset voltage temperature coefficient measured from t min to t max 3v/c ib input bias current v in = 0v -9 -6 a i os input offset current v in = 0v 0.1 0.6 a tci os input bias current temperature coefficient measured from t min to t max 2na/c cmrr common mode rejection ratio v cm = -0.15v to +3.5v (el8202,el8203) 70 95 db v cm = -0.15v to +3.5v (EL8403) 60 85 db cmir common mode input range v s - - 0.15 v s + - 1.5 v r in input resistance common mode 3.5 m ? c in input capacitance 0.5 pf avol open loop gain v out = +1.5v to +3.5v, r l = 1k ? to gnd 75 90 db v out = +1.5v to +3.5v, r l = 150 ? to gnd 80 db output characteristics r out output resistance a v = +1 30 m ? v op positive output voltage swing r l = 1k ? 4.85 4.9 v r l = 150 ? 4.6 4.7 v v on negative output voltage swing r l = 150 ? 100 150 mv r l = 1k ? (el8202,el8203) 25 50 mv r l = 1k ? (EL8403) 50 100 mv i out linear output current 65 ma i sc (source) short circuit current r l = 10 ? 60 80 ma i sc (sink) short circuit current r l = 10 ? 120 150 ma power supply psrr power supply rejection ratio v s + = 4.5v to 5.5v 70 95 db i s-on supply current - enabled (per amplifier) 5.6 6.2 ma i s-off supply current - disabled (per amplifier) el8202 only 40 90 a enable (el8202 only) t en enable time 200 ns t ds disable time 25 ns v ih-enb enable pin voltage for power-up 0.8 v v il-enb enable pin voltage for shut-down 2 v el8202, el8203, EL8403
4 i ih-enb enable pin input current high 8.6 a i il-enb enable pin input for current low 0.01 a ac performance bw -3db bandwidth a v = +1, r f = 0 ? , c l = 2.5pf 500 mhz a v = -1, r f = 1k ? , c l = 2.5pf 140 mhz a v = +2, r f = 1k ? , c l = 2.5pf 165 mhz a v = +10, r f = 1k ? , c l = 2.5pf 18 mhz bw 0.1db bandwidth a v = +1, r f = 0 ? , c l = 2.5pf 35 mhz peak peaking a v = +1, r l = 1k ? , c l = 2.5pf 2 db gbwp gain bandwidth product 200 mhz pm phase margin r l = 1k ? , c l = 2.5pf 55 sr slew rate a v = 2, r l = 100 ? , v out = 0.5v to 4.5v 500 600 v/s t r rise time 2.5v step , 20% - 80% 4 ns t f fall time 2.5v step , 20% - 80% 2 ns os overshoot 200mv step 10 % t pd propagation delay 200mv step 1 ns t s 0.1% settling time 200mv step 15 ns dg differential gain a v = +2, r f = 1k ? , r l = 150 ? 0.01 % dp differential phase a v = +2, r f = 1k ? , r l = 150 ? 0.01 e n input noise voltage f = 10khz 12 nv/ hz i n + positive input noise current f = 10khz 1.7 pa/ hz i n - negative input noise current f = 10khz 1.3 pa/ hz e s channel separation f = 100khz 95 db electrical specifications v s + = 5v, v s - = gnd, t a = 25c, v cm = 2.5v, r l to 2.5v, a v = 1, unless otherwise specified (continued) parameter description conditions min typ max unit pin descriptions el8202 (msop-10) el8203 (so-8, msop-8) EL8403 (so-14) EL8403 (qsop-16) name function 1, 5 3, 5 3, 5, 10, 12 3,5,12,14 in+ non-inverting input for each channel 2, 4 ce enable and disable i nput for each channel 3 4 11 13 vs- negative power supply 6, 10 2, 6 2, 6, 9, 13 2,6,11,15 in- inverting input for each channel 7, 9 1, 7 1, 7, 8, 14 1,7,10,16 out amplifier output for each channel 8 8 4 4 vs+ positive power supply el8202, el8203, EL8403
5 typical performance curves figure 1. frequency respo nse for various output voltage levels figure 2. small signal frequency response vs r f and r g figure 3. small signal frequency response for various non-inverting gains figure 4. small signal frequency response for various inverting gains figure 5. small signal frequency response for various non-inverting gains figure 6. small signal frequency response vs various r load 5 3 1 -1 -3 -5 1m 10m 100m 1g frequency (hz) gain (db) v s =5v a v =1 r l =1k ? c l =2.5pf 4 2 0 -2 -4 v op-p =200mv v op-p =1v v op-p =2v 5 3 1 -1 -3 -5 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) v s =5v a v =2 r l =1k ? c l =2.5pf r f =r g =2k ? r f =r g =500 ? r f =r g =1k ? 5 3 1 -1 -3 -5 1m 10m 100m 1g frequency (hz) normalized gain (db) a v =10 a v =1 v s =5v c l =2.5pf r l =1k ? a v =5 a v =2 4 2 0 -2 -4 4 2 0 -2 -4 -6 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) a v =-10 v s =5v c l =2.5pf r l =1k ? r f =1k ? a v =-1 a v =-5 5 3 1 -1 -3 -5 1m 10m 100m 1g frequency (hz) gain (db) r l =1k ? v s =5v a v =1 c l =2.5pf 4 2 0 -2 -4 r l =100 ? r l =500 ? 11 9 7 5 3 1 100k 1m 10m 100m 1g frequency (hz) gain (db) v s =5v a v =2 c l =2.5pf r f =r g =1k ? r l =500 ? r l =1k ? , 150 ? el8202, el8203, EL8403
6 figure 7. small signal frequency response vs c l figure 8. small signal frequency response for various c l figure 9. open loop gain and phase vs frequency figure 10. disabled output isolation frequency response figure 11. power supply rejection ratio vs frequency figure 12. small signal bandwidth vs supply voltage typical performance curves (continued) 5 3 1 -1 -3 -5 1m 10m 100m 1g frequency (hz) gain (db) c l =5.4pf c l =1.5pf v s =5v a v =1 r l =1k ? 4 3 0 -2 -4 c l =2.5pf 16 12 8 4 0 -4 100k 1m 10m 100m 1g frequency (hz) gain (db) v s =5v a v =2 r f =r g =1k ? c l =28.5pf c l =2.5pf 14 10 6 2 -2 c l =10pf c l =20pf 110 70 30 -10 -50 -90 1k 10k 1m 100m 1g frequency (hz) gain (db) r l =1k ? phase () -45 405 315 225 135 45 100k 10m r l =150 ? r l =150 ? r l =1k ? -10 -30 -50 -70 -90 -110 1k 10k 100k 100m 1g frequency (hz) gain (db) v s =5v a v =1 r l =1k ? 1m 10m -10 -30 -50 -70 -90 -110 1k 10k 10m 100m frequency (hz) psrr (db) 100k 1m psrr- psrr+ 600 400 350 550 200 150 3 3.5 4.5 5 5.5 v s (v) bandwidth (mhz) a v =1 500 300 250 4 r l =1k ? c l =2.5pf a v =2 450 100 el8202, el8203, EL8403
7 figure 13. ouput impedance vs frequency figure 14. small signal peaking vs supply voltage figure 15. common-mode rejection ratio vs frequency figure 16. supply current vs supply voltage (per channel) figure 17. harmonic distortion vs output voltage figure 18. harmonic distortion vs load resistance typical performance curves (continued) 100 10 1 0.1 0.01 10k 100k 1m 10m frequency (hz) impedance ( ? ) 100m 3.5 2 1.5 3 0 3 3.5 4.5 5 5.5 v s (v) peaking (db) r l =1k ? c l =1.5pf a v =1 a v =2 2.5 1 0.5 4 -15 -35 -55 -75 -95 -115 100k 1m 10m 100m frequency (hz) cmrr (db) 10 4 8 0 01 34 5.5 v s (v) i s (ma) 6 2 2 0.5 1.5 3.5 4.5 5 2.5 -60 -70 -80 -100 15 v op-p (v) distortion (dbc) v s =5v r l =1k ? c l =2.5pf a v =2 -90 34 2 h d 2 @ 1 0 m h z h d 2 @ 5 m h z h d 2 @ 1 m h z h d 3 @ 1 0 m h z h d 3 @ 5 m h z hd3@1mhz -70 -75 -90 -100 100 2k r load ( ? ) distortion (dbc) -95 1k v o =1v p-p for a v =1 v o =2v p-p for a v =2 -85 -80 h d 2 @ a v = 2 h d 2 @ a v = 1 h d 3 @ a v = 2 h d 3 @ a v = 1 v s =5v f=5mhz el8202, el8203, EL8403
8 figure 19. harmonic distortion vs frequency fi gure 20. voltage and current noise vs frequency figure 21. channel separation vs frequency (el8202 and el8203) figure 22. channel separation vs frequency (EL8403) figure 23. large signal transient response - rising figure 24. large signal transient response - falling typical performance curves (continued) -50 -70 -90 -60 -100 140 frequency (mhz) distortion (dbc) v s =5v r l =1k ? c l =2.5pf v o =1v p-p for a v =1 v o =2v p-p for a v =2 10 h d 2 @a v = 2 -80 h d 2 @ a v = 1 h d 3 @ a v = 2 h d 3 @ a v = 1 1k 100 1 10 100 10k 100k 10m frequency (hz) voltage noise (nv/ hz) current noise (pa/ hz), e n 10 1k 1m i n + i n - 0 -20 -40 -60 -80 -100 100k 1m 10m 100m 1g frequency (hz) channel separation (db) ch1<=>ch2 -10 -30 -50 -70 -90 0 -20 -40 -60 -80 -100 100k 1m 10m 100m 1g frequency (hz) channel separation (db) -10 -30 -50 -70 -90 ch1<=>ch3 ch2<=>ch4 ch1<=>ch2 ch1<=>ch4 ch2<=>ch3 2ns/div 1.5 2.5 3.5 v s =5v a v =1 r l =1k ? to 2.5v c l =5pf 2ns/div 1.5 2.5 3.5 v s =5v a v =1 r l =1k ? to 2.5v c l =5pf el8202, el8203, EL8403
9 figure 25. small signal transien t reponse figure 26. output swing figure 27. output swing figure 28. enabled responses (el8202) figure 29. disabled response (el8202) figure 30. package power dissipation vs ambient temperature typical performance curves (continued) 10ns/div 2.4 2.6 2.5 2.6 2.4 2.5 v out v in v s =5v, a v =1, r l =1k ? to 2.5v, c l = 2.5pf 2s/div 0 2.5 5 v s =5v, a v =5, r l =1k ? to 2.5v 2s/div 0 2.5 5 v s =5v, a v =5, r l =1k ? to 2.5v ch1, ch2, 1v/div, m=100ns ch2 ch1 enable input v out ch1, ch2, 0.5v/div, m=20ns ch2 ch1 enable input v out 486mw ja =206c/w msop8/10 625mw 1 0.9 0.8 0.6 0.4 0.1 0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) 125 85 jedec jesd51-3 low effective thermal conductivity test board 0.2 0.7 0.3 0.5 833mw j a = 1 2 0 c / w s o 1 4 633mw j a = 1 5 8 c / w ja =160c/w so8 qsop16 el8202, el8203, EL8403
10 simplified schematic diagram description of operat ion and application information product description the el8202, el8203 and EL8403 are wide bandwidth, single supply, low power and rail-to-rail output voltage feedback operational amplifiers. the amplifiers are internally compensated for closed loop gain of +1 of greater. connected in voltage follower mode and driving a 1k ? load, the el8202, el8203 and EL8403 have a -3db bandwidth of 500mhz. driving a 150 ? load, the bandwidth is about 350mhz while maintaining a 600v/us slew rate. the el8202 is available with a power down pin to reduce power to 30a typically while the amplifier is disabled. input, output and supply voltage range the el8202, el8203 and EL8403 have been designed to operate with a single supply voltage from 3v to 5.0v. split supplies can also be used as long as their total voltage is within 3v to 5.0v. the amplifiers have an input common mode voltage range from 0.15v below the negative supply (v s - pin) to within 1.5v of the positive supply (v s + pin). if the input signal is outside the abov e specified range, it will cause the output signal to be distorted. the output of the el8202, el8203 and EL8403 can swing rail to rail. as the load resistance becomes lower, the ability to drive close to each rail is reduced. for the load resistor 1k ? , the output swing is about 4.9v at a 5v supply. for the load resistor 150 ? , the output swing is about 4.6v. figure 31. package power dissipation vs ambient temperature typical performance curves (continued) 909mw 1.4 1.2 1 0.8 0.6 0.2 0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) 125 85 jedec jesd51-7 high effective thermal conductivity test board 0.4 j a = 8 8 c / w s o 1 4 ja =110c/w so8 893mw 870mw ja =115c/w msop8/10 ja =112c/w qsop16 1.136w in+ in- i 1 i 2 r 6 r 3 r 1 r 2 q 1 q 2 r 7 v bias1 q 5 q 6 r 8 q 7 q 8 r 9 q 3 q 4 r 4 r 5 v s- out v bias2 v s+ differential to drive generator single ended el8202, el8203, EL8403
11 choice of feedback resistor and gain bandwidth product for applications that require a gain of +1, no feedback resistor is required. just shor t the output pin to the inverting input pin. for gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. as this pole becomes smaller, the amplifier?s phase margin is reduced. this causes ringing in the time domain and peaking in the frequency domain. therefore, r f has some maximum value that should not be exceeded for optimum performance. if a large value of r f must be used, a small capacitor in the few pf range in parallel with r f can help to reduce the ringing and peaking at the expense of reducing the bandwidth. as far as the output stage of the amplifier is concerned, the output stage is also a gain stage with the load. r f and r g appear in parallel with r l for gains other than +1. as this combination gets smaller, the bandwidth falls off. consequently, r f also has a minimum value that should not be exceeded for optimum perfor mance. for gain of +1, r f =0 is optimum. for the gains other than +1, optimum response is obtained with r f between 300 ? to 1k ? . the el8202, el8203 and EL8403 have a gain bandwidth product of 200mhz. for gains 5, its bandwidth can be predicted by the following equation: video performance for good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as dc levels are changed at the output. this is especially difficult when driving a standard video load of 150 ? , because the change in output current with dc level. special circuitry has been in corporated in the el8202, el8203 and EL8403 to reduce the variation of the output impedance with the current output. this results in dg and dp specifications of 0.01% and 0.01 , while driving 150 ? at a gain of 2. driving high impedance loads would give a similar or better dg and dp performance. driving capacitive loads and cables the el8202, el8203 and EL8403 can drive 5pf loads in parallel with 1k ? with less than 5db of peaking at gain of +1. if less peaking is desired in applications, a small series resistor (usually between 5 ? to 50 ? ) can be placed in series with the output to eliminate most peaking. however, this will reduce the gain slightly. if the gain setting is greater than 1, the gain resistor r g can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. when used as a cable driver, double termination is always recommended for reflection-free performance. for those applications, a back-termination series resistor at the amplifier?s output will isolate th e amplifier from the cable and allow extensive capacitive drive. however, other applications may have high capacitive loads without a back-termination resistor. again, a small series resistor at the output can help to reduce peaking. disable/power-down the el8202 can be disabled and placed its output in a high impedance state. the turn off time is about 25ns and the turn on time is about 200ns. when disabled, the amplifier?s supply current is reduced to 40a typically, thereby effectively eliminating the power consumption. the amplifier?s power down can be controlled by standard ttl or cmos signal levels at the enable pin. the applied logic signal is relative to v s - pin. letting the enable pin float or applying a signal that is less than 0.8v above v s - will enable the amplifier. the amplifier will be disabled when the signal at enable pin is 2v above v s -. output drive capability the el8202, el8203 and EL8403 do not have internal short circuit protection circuitry. they have a typical short circuit current of 80ma sourcing and 150ma sinking for the output is connected to half way between the rails with a 10 ? resistor. if the output is s horted indefinitely, the power dissipation could easily increase such that the part will be destroyed. maximum reliability is maintained if the output current never exceeds 40ma. this limit is set by the design of the internal metal interconnections. power dissipation with the high output drive capability of the el8202, el8203 and EL8403. it is possible to exceed the 125 c absolute maximum junction temperature under certain load current conditions. therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. the maximum power dissipation allowed in a package is determined according to: where: t jmax = maximum junction temperature t amax = maximum ambient temperature ja = thermal resistance of the package the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the load, or: gain bw 200mhz = pd max t jmax t amax ? ja -------------------------------------------- - = el8202, el8203, EL8403
12 for sourcing: for sinking: where: v s = total supply voltage i smax = maximum quiescent supply current v outi = maximum output voltage of the application for each channel r loadi = load resistance tied to ground for each channel i loadi = load current for each channel by setting the two pd max equations equal to each other, we can solve the output current and r loadi to avoid the device overheat. power supply bypassing and printed circuit board layout as with any high frequency device, a good printed circuit board layout is necessary for optimum performance. lead lengths should be as short as possible. the power supply pin must be well bypassed to reduce the risk of oscillation. for normal single supply operation, where the v s - pin is connected to the ground plane, a single 4.7f tantalum capacitor in parallel with a 0. 1f ceramic capacitor from v s + to gnd will suffice. this same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. in this case, the v s - pin becomes the negative supply rail. for good ac performance, parasitic capacitance should be kept to a minimum. use of wire wound resistors should be avoided because of their additional series inductance. use of sockets should also be avoided if possible. sockets add parasitic inductance and capacitance that can result in compromised performanc e. minimizing parasitic capacitance at the amplifier?s inverting input pin is very important. the feedback resistor should be placed very close to the inverting input pin. strip line design techniques are recommended for the signal traces. typical applications video sync pulse remover many cmos analog to digital converters have a parasitic latch up problem when subjected to negative input voltage levels. since the sync tip contains no useful video information and it is a negativ e going pulse, we can chop it off. figure 32 shows a gain of 2 connections. figure 33 shows the complete input video signal applied at the input, as well as the output sig nal with the negative going sync pulse removed. multiplexer besides the normal power down usage, the enable pin of the el8202 can be used for mu ltiplexing applications. figure 34 shows two el8202 with the out puts tied together, driving a back terminated 75 ? video load. a 2v p-p 2mhz sine wave is applied to amp a and a 1v p-p 2mhz sine wave is applied to amp b. figure 33 shows the enable signal and the resulting output waveform at v out . observe the break- before-make operation of the multiplexing. amp a is on and v in1 is passed through to the output when the enable signal is low and turns off in about 25ns when the enable signal is high. about 200ns later, amp b turns on and v in2 is passed through to the output. the break-before-make operation ensures that more than one amplifier isn?t trying to drive the bus at the same time. pd max v s i smax v s v outi ? () v outi r li ----------------- + = pd max v s i smax v outi v s - ? () i loadi + = figure 32. sync pulse remover 5v 1k v out v in 75 ? + - 75 ? 1k 75 ? v s+ v s- figure 33. video signal 1v 0.5v 0v 1v 0.5v 0v m = 10s/div v out v in el8202, el8203, EL8403
13 single supply video line driver the el8202, el8203 and EL8403 are wideband rail-to-rail output op amplifiers with large output current, excellent dg, dp, and low distortion that allow them to drive video signals in low supply applications. figure 36 is the single supply non-inverting video line driver configuration and figure 37 is the inverting video ling driver configuration. the signal is ac coupled by c 1 . r 1 and r 2 are used to level shift the input and output to provide the largest output swing. r f and r g set the ac gain. c 2 isolates the virtual ground potential. r t and r 3 are the termination resistors for the line. c 1 , c 2 and c 3 are selected big enough to minimize the droop of the luminance signal. figure 34. two to one multiplexer +2.5v 1k 2mhz 75 ? + - 1k 75 ? -2.5v v out 75 ? 1v p-p b +2.5v 1k 2mhz + - 1k 75 ? -2.5v 2v p-p a enable figure 35. 0v -0.5v -1.5v -2.5v 1v 0v m = 50ns/div a enable b -1v figure 36. 5v single supply non inverting video line driver figure 37. single supply inverting video line driver figure 38. video line driver frequency response 5v r f v out v in 75 ? + - 75 ? 1k ? 75 ? c 3 470f r 3 c 1 47f r t 10k 10k r 2 r 1 1k ? r g c 2 220f 5v r f v out v in 75 ? - + 75 ? 500 ? 75 ? c 3 470f r 3 c 1 47f r t 10k 10k r 2 r 1 1k ? r g c 2 220f 5v 4 3 2 1 0 -1 -2 -3 -4 -5 -6 normalized gain (db) 100k 1m 10m 100m 500m frequency (hz) a v = -2 a v = 2 el8202, el8203, EL8403
14 so package outline drawing el8202, el8203, EL8403
15 msop package outline drawing el8202, el8203, EL8403
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com qsop package outline drawing note: the package drawing shown here may not be the latest version. to check the latest revision, please refer to the intersil w ebsite at http://www.intersil.com/design/packages/index.asp el8202, el8203, EL8403

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